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LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB flash with ISP/IAP, fast ports and 10-bit ADC
Rev. 04 -- 2 June 2009 Product data sheet
1. General description
The LPC2101/02/03 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service routines and DSP algorithms, this increases performance up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. Due to their tiny size and low power consumption, the LPC2101/02/03 are ideal for applications where miniaturization is a key requirement. A blend of serial communications interfaces ranging from multiple UARTs, SPI to SSP and two I2C-buses, combined with on-chip SRAM of 2 kB/4 kB/8 kB, make these devices very well suited for communication gateways and protocol converters. The superior performance also makes these devices suitable for use as math coprocessors. Various 32-bit and 16-bit timers, an improved 10-bit ADC, PWM features through output match on all timers, and 32 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems.
2. Features
2.1 Enhanced features
Enhanced features are available in parts LPC2101/02/03 labelled Revision A and higher: I Deep power-down mode with option to retain SRAM memory and/or RTC. I Three levels of flash Code Read Protection (CRP) implemented.
2.2 Key features
I 16-bit/32-bit ARM7TDMI-S microcontroller in tiny LQFP48 and HVQFN48 packages. I 2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip flash program memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation. I ISP/IAP via on-chip bootloader software. Single flash sector or full chip erase in 100 ms and programming of 256 bytes in 1 ms. I EmbeddedICE-RT offers real-time debugging with the on-chip RealMonitor software. I The 10-bit ADC provides eight analog inputs, with conversion times as low as 2.44 s per channel and dedicated result registers to minimize interrupt overhead. I Two 32-bit timers/external event counters with combined seven capture and seven compare channels.
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
I Two 16-bit timers/external event counters with combined three capture and seven compare channels. I Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz clock input. I Multiple serial interfaces including two UARTs (16C550), two Fast I2C-buses (400 kbit/s), SPI and SSP with buffering and variable data length capabilities. I Vectored interrupt controller with configurable priorities and vector addresses. I Up to thirty-two, 5 V tolerant fast general purpose I/O pins. I Up to 13 edge or level sensitive external interrupt pins available. I 70 MHz maximum CPU clock available from programmable on-chip PLL with a possible input frequency of 10 MHz to 25 MHz and a settling time of 100 s. I On-chip integrated oscillator operates with an external crystal in the range from 1 MHz to 25 MHz. I Power saving modes include Idle mode, Power-down mode with RTC active, and Power-down mode. I Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization. I Processor wake-up from Power-down and Deep power-down (Revision A and higher) mode via external interrupt or RTC.
3. Ordering information
Table 1. Ordering information Package Name LPC2101FBD48 LPC2102FBD48 LPC2103FBD48 LPC2102FHN48 LPC2103FHN48 LQFP48 LQFP48 LQFP48 HVQFN48 HVQFN48 Description plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 6 x 6 x 0.85 mm Version SOT313-2 SOT313-2 SOT313-2 SOT619-7 SOT619-7 SOT778-3 Type number
LPC2103FHN48H HVQFN48
3.1 Ordering options
Table 2. Ordering options Flash memory 8 kB 16 kB 32 kB 16 kB 32 kB 32 kB RAM 2 kB 4 kB 8 kB 4 kB 8 kB 8 kB ADC 8 inputs 8 inputs 8 inputs 8 inputs 8 inputs 8 inputs Temperature range (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85
(c) NXP B.V. 2009. All rights reserved.
Type number LPC2101FBD48 LPC2102FBD48 LPC2103FBD48 LPC2102FHN48 LPC2103FHN48 LPC2103FHN48H
LPC2101_02_03_4
Product data sheet
Rev. 04 -- 2 June 2009
2 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
4. Block diagram
TMS TRST TCK TDI TDO XTAL2 VDD(3V3) VDD(1V8) XTAL1 RST VSS
LPC2101/2102/2103
HIGH SPEED GENERAL PURPOSE I/O
TEST/DEBUG INTERFACE
P0[31:0]
8 kB BOOT ROM
ARM7TDMI-S
AHB BRIDGE
PLL system clock
SYSTEM FUNCTIONS
ARM7 local bus
VECTORED INTERRUPT CONTROLLER
AMBA AHB (Advanced High-performance Bus) INTERNAL SRAM CONTROLLER MEMORY ACCELERATOR
2 kB/4 kB/ 8 kB SRAM
8 kB/16 kB/ 32 kB FLASH
AHB TO APB BRIDGE APB (ARM peripheral bus)
EINT2 to EINT0(1) 3 x CAP0(1) 4 x CAP1(1) 3 x CAP2(1) 3 x MAT0(1) 4 x MAT1(1) 3 x MAT2(1) 4 x MAT3(1) AD0[7:0]
EXTERNAL INTERRUPTS
I2C-BUS SERIAL INTERFACES 0 AND 1
SCL0, SCL1(1) SDA0, SDA1(1) SCK0, SCK1(1)
CAPTURE/COMPARE EXTERNAL COUNTER TIMER 0/TIMER 1/ TIMER 2/TIMER 3
SPI AND SSP SERIAL INTERFACES
MOSI0, MOSI1(1) MISO0, MISO1(1) SSEL0, SSEL1(1) TXD0, TXD1(1)
ADC
UART0/UART1
RXD0, RXD1(1)
DSR1, CTS1, RTS1, DTR1 DCD1, RI1
RTCX1 RTCX2 VBAT
P0[31:0]
GENERAL PURPOSE I/O
REAL-TIME CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
002aab814
(1) Pins shared with GPIO.
Fig 1.
Block diagram
LPC2101_02_03_4
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Product data sheet
Rev. 04 -- 2 June 2009
3 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
5. Pinning information
5.1 Pinning
37 P0.12/DSR1/MAT1.0/AD0.5 36 P0.11/CTS1/CAP1.1/AD0.4 35 P0.10/RTS1/CAP1.0/AD0.3 34 P0.24/AD0.2 33 P0.23/AD0.1 32 P0.22/AD0.0 31 VSSA 30 P0.9/RXD1/MAT2.2 29 P0.8/TXD1/MAT2.1 28 P0.7/SSEL0/MAT2.0 27 DBGSEL 26 RTCK 25 RTCX2 P0.0/TXD0/MAT3.1 13 P0.1/RXD0/MAT3.2 14 P0.30/TDI/MAT3.3 15 P0.31/TDO 16 VDD(3V3) 17 P0.2/SCL0/CAP0.0 18 VSS 19 RTCX1 20 P0.3/SDA0/MAT0.0 21 P0.4/SCK0/CAP0.1 22 P0.5/MISO0/MAT0.1 23 P0.6/MOSI0/CAP0.2 24
002aab821
44 P0.14/DCD1/SCK1/EINT1
46 P0.16/EINT0/MAT0.2
41 P0.13/DTR1/MAT1.1
48 P0.18/CAP1.3/SDA1
47 P0.17/CAP1.2/SCL1
45 P0.15/RI1/EINT2
P0.19/MAT1.2/MISO1 P0.20/MAT1.3/MOSI1 P0.21/SSEL1/MAT3.0 VBAT VDD(1V8) RST VSS P0.27/TRST/CAP2.0 P0.28/TMS/CAP2.1
1 2 3 4 5 6 7 8 9
LPC2101FBD48 LPC2102FBD48 LPC2103FBD48
P0.29/TCK/CAP2.2 10 XTAL1 11 XTAL2 12
Fig 2.
Pin configuration (LQFP48)
LPC2101_02_03_4
38 P0.25/AD0.6
39 P0.26/AD0.7
40 VDD(3V3)
42 VDDA
43 VSS
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 2 June 2009
4 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
terminal 1 index area P0.19/MAT1.2/MISO1 P0.20/MAT1.3/MOSI1 P0.21/SSEL1/MAT3.0 VBAT VDD(1V8) RST VSS P0.27/TRST/CAP2.0 P0.28/TMS/CAP2.1 1 2 3 4 5 6 7 8 9
37 P0.12/DSR1/MAT1.0/AD0.5 36 P0.11/CTS1/CAP1.1/AD0.4 35 P0.10/RTS1/CAP1.0/AD0.3 34 P0.24/AD0.2 33 P0.23/AD0.1 32 P0.22/AD0.0 31 VSSA 30 P0.9/RXD1/MAT2.2 29 P0.8/TXD1/MAT2.1 28 P0.7/SSEL0/MAT2.0 27 DBGSEL 26 RTCK 25 RTCX2 P0.6/MOSI0/CAP0.2 24
002aad918
44 P0.14/DCD1/SCK1/EINT1
46 P0.16/EINT0/MAT0.2
41 P0.13/DTR1/MAT1.1
48 P0.18/CAP1.3/SDA1
47 P0.17/CAP1.2/SCL1
45 P0.15/RI1/EINT2
40 VDD(3V3) 39 P0.26/AD0.7 P0.3/SDA0/MAT0.0 21 P0.4/SCK0/CAP0.1 22
LPC2102FHN48 LPC2103FHN48 LPC2103FHN48H
P0.29/TCK/CAP2.2 10 XTAL1 11 XTAL2 12 P0.0/TXD0/MAT3.1 13 P0.1/RXD0/MAT3.2 14 P0.30/TDI/MAT3.3 15 P0.31/TDO 16 VDD(3V3) 17 P0.2/SCL0/CAP0.0 18 VSS 19 RTCX1 20 P0.5/MISO0/MAT0.1 23
Transparent top view
Fig 3.
Pin configuration (HVQFN48)
LPC2101_02_03_4
38 P0.25/AD0.6
43 VSS 42 VDDA
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Product data sheet
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5 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
5.2 Pin description
Table 3. Symbol P0.0 to P0.31 Pin description Pin Type I/O Description Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. A total of 31 pins of the Port 0 can be used as general purpose bidirectional digital I/Os while P0.31 is an output only pin. The operation of port 0 pins depends upon the pin function selected via the pin connect block. P0.0 -- General purpose input/output digital pin. TXD0 -- Transmitter output for UART0. MAT3.1 -- PWM output 1 for Timer 3. P0.1 -- General purpose input/output digital pin. RXD0 -- Receiver input for UART0. MAT3.2 -- PWM output 2 for Timer 3. P0.2 -- General purpose input/output digital pin. Output is open-drain. SCL0 -- I2C0 clock Input/output. Open-drain output (for I2C-bus compliance). CAP0.0 -- Capture input for Timer 0, channel 0. P0.3 -- General purpose input/output digital pin. Output is open-drain. SDA0 -- I2C0 data input/output. Open-drain output (for I2C-bus compliance). MAT0.0 -- PWM output for Timer 0, channel 0. Output is open-drain. P0.4 -- General purpose input/output digital pin. SCK0 -- Serial clock for SPI0. SPI clock output from master or input to slave. CAP0.1 -- Capture input for Timer 0, channel 1. P0.5 -- General purpose input/output digital pin. MISO0 -- Master In Slave Out for SPI0. Data input to SPI master or data output from SPI slave. MAT0.1 -- PWM output for Timer 0, channel 1. P0.6 -- General purpose input/output digital pin. MOSI0 -- Master Out Slave In for SPI0. Data output from SPI master or data input to SPI slave. CAP0.2 -- Capture input for Timer 0, channel 2. P0.7 -- General purpose input/output digital pin. SSEL0 -- Slave Select for SPI0. Selects the SPI interface as a slave. MAT2.0 -- PWM output for Timer 2, channel 0. P0.8 -- General purpose input/output digital pin. TXD1 -- Transmitter output for UART1. MAT2.1 -- PWM output for Timer 2, channel 1. P0.9 -- General purpose input/output digital pin. RXD1 -- Receiver input for UART1. MAT2.2 -- PWM output for Timer 2, channel 2. P0.10 -- General purpose input/output digital pin. RTS1 -- Request to Send output for UART1. CAP1.0 -- Capture input for Timer 1, channel 0. AD0.3 -- ADC 0, input 3.
P0.0/TXD0/ MAT3.1
13[1]
I/O O O
P0.1/RXD0/ MAT3.2
14[1]
I/O I O
P0.2/SCL0/ CAP0.0
18[2]
I/O I/O I
P0.3/SDA0/ MAT0.0
21[2]
I/O I/O O
P0.4/SCK0/ CAP0.1
22[1]
I/O I/O I
P0.5/MISO0/ MAT0.1
23[1]
I/O I/O O
P0.6/MOSI0/ CAP0.2
24[1]
I/O I/O I
P0.7/SSEL0/ MAT2.0
28[1]
I/O I O
P0.8/TXD1/ MAT2.1
29[1]
I/O O O
P0.9/RXD1/ MAT2.2
30[1]
I/O I O
P0.10/RTS1/ CAP1.0/AD0.3
35[3]
I/O O I I
LPC2101_02_03_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 2 June 2009
6 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Table 3. Symbol
Pin description ...continued Pin 36[3] Type I/O I I I Description P0.11 -- General purpose input/output digital pin. CTS1 -- Clear to Send input for UART1. CAP1.1 -- Capture input for Timer 1, channel 1. AD0.4 -- ADC 0, input 4. P0.12 -- General purpose input/output digital pin. DSR1 -- Data Set Ready input for UART1. MAT1.0 -- PWM output for Timer 1, channel 0. AD0.5 -- ADC 0, input 5. P0.13 -- General purpose input/output digital pin. DTR1 -- Data Terminal Ready output for UART1. MAT1.1 -- PWM output for Timer 1, channel 1. P0.14 -- General purpose input/output digital pin. DCD1 -- Data Carrier Detect input for UART1. SCK1 -- Serial Clock for SPI1. SPI clock output from master or input to slave. EINT1 -- External interrupt 1 input. P0.15 -- General purpose input/output digital pin. RI1 -- Ring Indicator input for UART1. EINT2 -- External interrupt 2 input. P0.16 -- General purpose input/output digital pin. EINT0 -- External interrupt 0 input. MAT0.2 -- PWM output for Timer 0, channel 2. P0.17 -- General purpose input/output digital pin. The output is not open-drain. CAP1.2 -- Capture input for Timer 1, channel 2. SCL1 -- I2C1 clock Input/output. This pin is an open-drain output if I2C1 function is selected in the pin connect block. P0.18 -- General purpose input/output digital pin. The output is not open-drain. CAP1.3 -- Capture input for Timer 1, channel 3. SDA1 -- I2C1 data Input/output. This pin is an open-drain output if I2C1 function is selected in the pin connect block. P0.19 -- General purpose input/output digital pin. MAT1.2 -- PWM output for Timer 1, channel 2. MISO1 -- Master In Slave Out for SSP. Data input to SSP master or data output from SSP slave. P0.20 -- General purpose input/output digital pin. MAT1.3 -- PWM output for Timer 1, channel 3. MOSI1 -- Master Out Slave for SSP. Data output from SSP master or data input to SSP slave. P0.21 -- General purpose input/output digital pin. SSEL1 -- Slave Select for SPI1. Selects the SPI interface as a slave. MAT3.0 -- PWM output for Timer 3, channel 0.
P0.11/CTS1/ CAP1.1/AD0.4
P0.12/DSR1/ MAT1.0/AD0.5
37[3]
I/O I O I
P0.13/DTR1/ MAT1.1
41[1]
I/O O O
P0.14/DCD1/ SCK1/EINT1
44[4][5]
I/O I I/O I
P0.15/RI1/ EINT2
45[4]
I/O I I
P0.16/EINT0/ MAT0.2
46[4]
I/O I O
P0.17/CAP1.2/ SCL1
47[6]
I/O I I/O
P0.18/CAP1.3/ SDA1
48[6]
I/O I I/O
P0.19/MAT1.2/ MISO1
1[1]
I/O O I/O
P0.20/MAT1.3/ MOSI1
2[1]
I/O O I/O
P0.21/SSEL1/ MAT3.0
3[1]
I/O I O
LPC2101_02_03_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 2 June 2009
7 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Table 3. Symbol
Pin description ...continued Pin 32[3] 33[3] 34[3] 38[3] 39[3] 8[1] Type I/O I I/O I I/O I I/O I I/O I I/O I I Description P0.22 -- General purpose input/output digital pin. AD0.0 -- ADC 0, input 0. P0.23 -- General purpose input/output digital pin. AD0.1 -- ADC 0, input 1. P0.24 -- General purpose input/output digital pin. AD0.2 -- ADC 0, input 2. P0.25 -- General purpose input/output digital pin. AD0.6 -- ADC 0, input 6. P0.26 -- General purpose input/output digital pin. AD0.7 -- ADC 0, input 7. P0.27 -- General purpose input/output digital pin. TRST -- Test Reset for JTAG interface. If DBGSEL is HIGH, this pin is automatically configured for use with EmbeddedICE (Debug mode). CAP2.0 -- Capture input for Timer 2, channel 0. P0.28 -- General purpose input/output digital pin. TMS -- Test Mode Select for JTAG interface. If DBGSEL is HIGH, this pin is automatically configured for use with EmbeddedICE (Debug mode). CAP2.1 -- Capture input for Timer 2, channel 1. P0.29 -- General purpose input/output digital pin. TCK -- Test Clock for JTAG interface. This clock must be slower than 16 of the CPU clock (CCLK) for the JTAG interface to operate. If DBGSEL is HIGH, this pin is automatically configured for use with EmbeddedICE (Debug mode). CAP2.2 -- Capture input for Timer 2, channel 2. P0.30 -- General purpose input/output digital pin. TDI -- Test Data In for JTAG interface. If DBGSEL is HIGH, this pin is automatically configured for use with EmbeddedICE (Debug mode). MAT3.3 -- PWM output 3 for Timer 3. P0.31 -- General purpose output only digital pin. TDO -- Test Data Out for JTAG interface. If DBGSEL is HIGH, this pin is automatically configured for use with EmbeddedICE (Debug mode). Input to the RTC oscillator circuit. Input voltage must not exceed 1.8 V. Output from the RTC oscillator circuit. Returned test clock output: Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional pin with internal pull-up. Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. Output from the oscillator amplifier. Debug select: When LOW, the part operates normally. When externally pulled HIGH at reset, P0.27 to P0.31 are configured as JTAG port, and the part is in Debug mode[9]. Input with internal pull-down. External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
(c) NXP B.V. 2009. All rights reserved.
P0.22/AD0.0 P0.23/AD0.1 P0.24/AD0.2 P0.25/AD0.6 P0.26/AD0.7 P0.27/TRST/ CAP2.0
P0.28/TMS/ CAP2.1
9[1]
I/O I I
P0.29/TCK/ CAP2.2
10[1]
I/O I
I P0.30/TDI/ MAT3.3 15[1] I/O I O P0.31/TDO 16[1] O O RTCX1 RTCX2 RTCK 20[7][8] 25[7][8] 26[7] I O I/O
XTAL1 XTAL2 DBGSEL
11 12 27
I O I
RST
6
I
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LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Table 3. Symbol VSS VSSA VDDA
Pin description ...continued Pin 7, 19, 43 31 42 Type I I I Description Ground: 0 V reference. Analog ground: 0 V reference. This should be nominally the same voltage as VSS but should be isolated to minimize noise and error. Analog 3.3 V power supply: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. The level on this pin also provides a voltage reference level for the ADC. 1.8 V core power supply: This is the power supply voltage for internal circuitry and the on-chip PLL. 3.3 V pad power supply: This is the power supply voltage for the I/O ports. RTC power supply: 3.3 V on this pin supplies the power to the RTC.
VDD(1V8) VDD(3V3) VBAT
[1] [2] [3]
5 17, 40 4
I I I
5 V tolerant (if VDD(3V3) and VDDA 3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. Open-drain 5 V tolerant (if VDD(3V3) and VDDA 3.0 V) digital I/O I2C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output functionality. Open-drain configuration applies to ALL functions on that pin. 5 V tolerant (if VDD(3V3) and VDDA 3.0 V) pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital section of the pad is disabled. 5 V tolerant (if VDD(3V3) and VDDA 3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. A LOW level during reset on pin P0.14 is considered as an external hardware request to start the ISP command handler. Open-drain 5 V tolerant (if VDD(3V3) and VDDA 3.0 V) digital I/O I2C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output functionality. Open-drain configuration applies only to I2C function on that pin. Pad provides special analog functionality. For lowest power consumption, pin should be left floating when the RTC is not used. See LPC2101/02/03 User manual UM10161 for details.
[4] [5] [6] [7] [8] [9]
LPC2101_02_03_4
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Product data sheet
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9 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
6. Functional description
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:
* The standard 32-bit ARM set. * A 16-bit Thumb set.
The Thumb set's 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM's performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. The particular flash implementation in the LPC2101/02/03 allows for full speed execution also in ARM mode. It is recommended to program performance critical and short code sections in ARM mode. The impact on the overall code size will be minimal but the speed can be increased by 30 % over Thumb mode.
6.2 On-chip flash program memory
The LPC2101/02/03 incorporate a 8 kB, 16 kB or 32 kB flash memory system respectively. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed in system via the serial port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. The entire flash memory is available for user code as the bootloader resides in a separate memory. The LPC2101/02/03 flash memory provides a minimum of 100,000 erase/write cycles and 20 years of data-retention memory.
LPC2101_02_03_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
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10 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
6.3 On-chip static RAM
On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2101/02/03 provide 2 kB, 4 kB or 8 kB of static RAM.
6.4 Memory map
The LPC2101/02/03 memory map incorporates several distinct regions, as shown in Figure 4. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either flash memory (the default) or on-chip static RAM. This is described in Section 6.17 "System control".
4.0 GB AHB PERIPHERALS 3.75 GB APB PERIPHERALS 3.5 GB
0xFFFF FFFF 0xF000 0000 0xE000 0000
3.0 GB RESERVED ADDRESS SPACE
0xC000 0000
2.0 GB BOOT BLOCK RESERVED ADDRESS SPACE
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF 0x4000 2000 0x4000 1FFF
8 kB ON-CHIP STATIC RAM (LPC2103) 4 kB ON-CHIP STATIC RAM (LPC2102) 2 kB ON-CHIP STATIC RAM (LPC2101) 1.0 GB RESERVED ADDRESS SPACE 32 kB ON-CHIP NON-VOLATILE MEMORY (LPC2103) 16 kB ON-CHIP NON-VOLATILE MEMORY (LPC2102) 8 kB ON-CHIP NON-VOLATILE MEMORY (LPC2101)
0x4000 1000 0x4000 0FFF 0x4000 0800 0x4000 07FF 0x4000 0000 0x0000 8000 0x0000 7FFF 0x0000 4000 0x0000 3FFF 0x0000 2000 0x0000 1FFF 0x0000 0000
002aab822
0.0 GB
Fig 4.
LPC2101/02/03 memory map
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6.5 Interrupt controller
The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored IRQ, and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine does not need to branch into the interrupt service routine but can run from the interrupt vector location. If more than one request is assigned to the FIQ class, the FIQ service routine will read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active.
6.5.1 Interrupt sources
Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.
6.6 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. The pin control module with its pin select registers defines the functionality of the microcontroller in a given hardware environment. After reset all pins of Port 0 are configured as input with the following exceptions: If the DBGSEL pin is HIGH (Debug mode enabled), the JTAG pins will assume their JTAG functionality for use with EmbeddedICE and cannot be configured via the pin connect block.
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6.7 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins. LPC2101/02/03 introduce accelerated GPIO functions over prior LPC2000 devices:
* GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing. * Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
* All GPIO registers are byte addressable. * Entire port value can be written in one instruction.
6.7.1 Features
* Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
* Direction control of individual bits. * Separate control of output set and clear. * All I/O default to inputs after reset. 6.8 10-bit ADC
The LPC2101/02/03 contain one ADC. It is a single 10-bit successive approximation ADC with eight channels.
6.8.1 Features
* * * * *
Measurement range of 0 V to 3.3 V. Each converter capable of performing more than 400,000 10-bit samples per second. Burst conversion mode for single or multiple inputs. Optional conversion on transition on input pin or Timer Match signal. Every analog input has a dedicated result register to reduce interrupt overhead.
6.9 UARTs
The LPC2101/02/03 each contain two UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface. Compared to previous LPC2000 microcontrollers, UARTs in LPC2101/02/03 include a fractional baud rate generator for both UARTs. Standard baud rates such as 115200 can be achieved with any crystal frequency above 2 MHz.
6.9.1 Features
* 16 byte Receive and Transmit FIFOs. * Register locations conform to 16C550 industry standard. * Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
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* Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
* Transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs.
* UART1 is equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS).
6.10 I2C-bus serial I/O controllers
The LPC2101/02/03 each contain two I2C-bus controllers. The I2C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line (SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., LCD driver) or a transmitter with the capability to both receive and send information such as serial memory. Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2101/02/03 supports bit rates up to 400 kbit/s (Fast I2C-bus).
6.10.1 Features
* * * * * *
Compliant with standard I2C-bus interface. Easy to configure as Master, Slave, or Master/Slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. one serial bus.
* Serial clock synchronization allows devices with different bit rates to communicate via * Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
* The I2C-bus can also be used for test and diagnostic purposes. 6.11 SPI serial I/O controller
The LPC2101/02/03 each contain one SPI controller. The SPI is a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master.
6.11.1 Features
* Compliant with SPI specification. * Synchronous, Serial, Full Duplex, Communication.
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* Combined SPI master and slave. * Maximum data bit rate of one eighth of the input clock rate. 6.12 SSP serial I/O controller
The LPC2101/02/03 each contain one SSP. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. However, only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to 16 bits flowing from the master to the slave and from the slave to the master. Often only one of these data streams carries meaningful data.
6.12.1 Features
* Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor's Microwire buses
* * * *
Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive Four bits to 16 bits per frame
6.13 General purpose 32-bit timers/external event counters
The Timer/Counter is designed to count cycles of the Peripheral Clock (PCLK) or an externally supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with `or' and `and', as well as `broadcast' functions among them. The LPC2101/02/03 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs or used as external interrupts.
6.13.1 Features
* A 32-bit timer/counter with a programmable 32-bit prescaler. * External event counter or timer operation. * Four 32-bit capture channels per timer/counter that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate an interrupt.
* Four 32-bit match registers that allow:
- Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation.
* Four external outputs per timer/counter corresponding to match registers, with the
following capabilities: - Set LOW on match.
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- Set HIGH on match. - Toggle on match. - Do nothing on match.
6.14 General purpose 16-bit timers/external event counters
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes three capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with `or' and `and', as well as `broadcast' functions among them. The LPC2101/02/03 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs or used as external interrupts.
6.14.1 Features
* Two 16-bit timer/counters with a programmable 16-bit prescaler. * External event counter or timer operation. * Three 16-bit capture channels that can take a snapshot of the timer value when an
input signal transitions. A capture event may also optionally generate an interrupt.
* Four 16-bit match registers that allow:
- Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation.
* Four external outputs per timer/counter corresponding to match registers, with the
following capabilities: - Set LOW on match. - Set HIGH on match. - Toggle on match. - Do nothing on match.
6.15 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to `feed' (or reload) the watchdog within a predetermined amount of time.
6.15.1 Features
* Internally resets chip if not periodically reloaded. * Debug mode. * Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
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* * * *
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate watchdog reset. Programmable 32-bit timer with internal pre-scaler. Selectable time period from (TPCLK x 256 x 4) to (TPCLK x 232 x 4) in multiples of TPCLK x 4.
6.16 Real-time clock
The Real-Time Clock (RTC) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode).
6.16.1 Features
* Measures the passage of time to maintain a calendar and clock. * Ultra-low power design to support battery powered systems. * Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day
of Year.
* Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the
external crystal/oscillator input at XTAL1. The programmable reference clock divider allows fine adjustment of the RTC.
* Dedicated power supply pin can be connected to a battery or the main 3.3 V. 6.17 System control
6.17.1 Crystal oscillator
The on-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz. The oscillator output frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is running and connected. Refer to Section 6.17.2 "PLL" and Section 10.1 "XTAL1 input" for additional information.
6.17.2 PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 70 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s.
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6.17.3 Reset and wake-up timer
Reset has two sources on the LPC2101/02/03: the RST pin and watchdog reset. The RST pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the wake-up timer (see wake-up timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip flash controller has completed its initialization. When the internal reset is removed, the processor begins executing at address 0, which is the reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined reset values. The wake-up timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down and Deep power-down mode, any wake-up of the processor from the Power-down modes makes use of the wake-up timer. The wake-up timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.
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6.17.4 Code security (Code Read Protection - CRP)
This feature of the LPC2101/02/03 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. Implemented in bootloader code version 2.21 are three levels of the Code Read Protection: 1. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased. 2. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P0.14 pin, too. It is up to the user's application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0.
CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.
Remark: Parts LPC2101/02/03 Revision `-' have CRP2 enabled only (bootloader code version 2.2).
6.17.5 External interrupt inputs
The LPC2101/02/03 include up to three edge or level sensitive external interrupt inputs as selectable pin functions. When the pins are combined, external events can be processed as three independent interrupt signals. The external interrupt inputs can optionally be used to wake-up the processor from Power-down mode and Deep power-down mode. Additionally all 10 capture input pins can also be used as external interrupts without the option to wake the device up from Power-down mode.
6.17.6 Memory mapping control
The memory mapping control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip flash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts.
6.17.7 Power control
The LPC2101/02/03 supports three reduced power modes: Idle mode, Power-down mode, and Deep power-down mode.
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In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero. Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip RTC will enable the microcontroller to have the RTC active during Power-down mode. Power-down current is increased with RTC active. However, it is significantly lower than in Idle mode. In Deep-power down mode all power is removed from the internal chip logic except for the RTC module, the I/O ports, the SRAM, and the 32 kHz external oscillator. For additional power savings, SRAM and the 32 kHz oscillator can be powered down individually. The Deep power-down mode produces the lowest possible power consumption without actually removing power from the entire chip. In Deep power-down mode, the contents of registers and memory are not preserved except for SRAM, if selected, and three general purpose registers. Therefore, to resume operations, a full chip reset process is required. A power selector module switches the RTC power supply from VBAT to VDD(1V8) whenever the core voltage is present on pin VDD(1V8) to conserve battery power. A power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings during Active and Idle mode.
6.17.8 APB
The APB divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first is to provide peripherals with the desired PCLK via APB so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the APB may be slowed down to 12 to 14 of the processor clock rate. Because the APB must work properly at power-up (and its timing cannot be altered if it does not work since the APB divider control registers reside on the APB), the default condition at reset is for the APB to run at 14 of the processor clock rate. The second purpose of the APB divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. Because the APB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode.
6.18 Emulation and debugging
The LPC2101/02/03 support emulation and debugging via a JTAG serial port.
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6.18.1 EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol converter. The EmbeddedICE protocol converter converts the remote debug protocol commands to the JTAG data needed to access the ARM core. The ARM core has a debug communication channel function built-in. The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The debug communication channel is accessed as a coprocessor 14 by the program running on the ARM7TDMI-S core. The debug communication channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The debug communication channel data and control registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock (TCK) must be slower than 16 of the CPU clock (CCLK) for the JTAG interface to operate.
6.18.2 RealMonitor
RealMonitor is a configurable software module, developed by ARM Inc., which enables real time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2101/02/03 contain a specific configuration of RealMonitor software programmed into the on-chip boot ROM memory.
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7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(1V8) VDD(3V3) VDDA Vi(VBAT) VIA VI Parameter supply voltage (1.8 V) supply voltage (3.3 V) analog 3.3 V pad supply voltage input voltage on pin VBAT analog input voltage input voltage 5 V tolerant I/O pins other I/O pins IDD ISS Tstg Ptot(pack) supply current ground current storage temperature total power dissipation (per package) based on package heat transfer, not device power consumption Human Body Model (HBM) Machine Model (MM) Charged Device Model (CDM)
[1]
Conditions
[2] [3]
Min -0.5 -0.5 -0.5 -0.5
[4] [5][6]
Max +2.5 +4.6 +4.6 +4.6 +5.1 +6.0
Unit V V V V V V
for the RTC
-0.5 -0.5 -0.5 -65 -
[5] [8] [10] [11]
VDD + 0.5[7] V 100[9] 100[9] +150 1.5 mA mA C W
VESD
electrostatic discharge voltage
-4000 -200 -800
+4000 +200 +800
V[12] V[13] V[14]
The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Core and internal rail. External rail. On ADC related pins. Including voltage on outputs in 3-state mode. Only valid when the VDD(3V3) supply voltage is present. Not to exceed 4.6 V. Per supply pin. The peak current is limited to 25 times the corresponding maximum current.
[2] [3] [4] [5] [6] [7] [8] [9]
[10] Per ground pin. [11] Dependent on package type. [12] Performed per AEC-Q100-002. [13] Performed per AEC-Q100-003. [14] Performed per AEC-Q100-011.
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8. Static characteristics
Table 5. Static characteristics Tamb= -40 C to +85 C for commercial applications, unless otherwise specified. Symbol VDD(1V8) VDD(3V3) VDDA Vi(VBAT) Parameter supply voltage (1.8 V) supply voltage (3.3 V) analog 3.3 V pad supply voltage input voltage on pin VBAT LOW-level input current HIGH-level input current OFF-state output current I/O latch-up current input voltage VI = 0 V; no pull-up VI = VDD(3V3); no pull-down VO = 0 V, VO = VDD(3V3); no pull-up/down -(0.5VDD(3V3)) < VI < (1.5VDD(3V3)); Tj < 125 C VI pin configured to provide a digital function; VDD(3V3) and VDDA 3.0 V pin configured to provide a digital function; VDD(3V3) and VDDA < 3.0 V VO VIH VIL Vhys VOH VOL IOH IOL IOHS output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current HIGH-level short-circuit output current LOW-level short-circuit output current pull-down current IOH = -4 mA IOL = -4 mA VOH = VDD(3V3) - 0.4 V VOL = 0.4 V VOH = 0 V
[10] [7][8] [9] [7][8] [9]
Conditions
[2]
Min 1.65 2.6[4] 2.6[5] 2.0[6]
Typ[1] 1.8 3.3 3.3 3.3
Max 1.95 3.6 3.6 3.6
Unit V V V V
[3]
Standard port pins, RST, RTCK IIL IIH IOZ Ilatch 0 0 0 2.0 0.4 3 3 3 100 5.5 VDD(3V3) VDD(3V3) 0.8 0.4 -45 A A A mA V V V V V V V V mA mA mA
output active
VDD(3V3) - 0.4 -4 4 -
[10]
[10]
[10]
[11]
IOLS
VOL = VDDA
[11]
-
-
50
mA
Ipd
VI = 5 V[12]
10
50
150
A
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Table 5. Static characteristics ...continued Tamb= -40 C to +85 C for commercial applications, unless otherwise specified. Symbol Ipu Parameter pull-up current Conditions VI = 0 V VDD(3V3) < VI < 5 IDD(CORE) core supply current Active mode; code V[12]
[13]
Min -15 0
Typ[1] -50 0
Max -85 0
Unit A A
while(1){}
executed from flash; all peripherals enabled via PCONP register but not configured to run; CCLK = 70 MHz VDD(1V8) = 1.8 V; Tamb = 25 C Power-down mode; VDD(1V8) = 1.8 V; Tamb = 25 C VDD(1V8) = 1.8 V; Tamb = 85 C Deep power-down mode; RTC off; SRAM off; Tamb = 25 C Vi(VBAT) = 3.3 V; VDD(1V8) = 1.8 V IBAT battery supply current Active mode; CCLK = 70 MHz; PCLK = 17.5 MHz; PCLK enabled to RTCK; RTC clock = 32 kHz (from RTCX pins); Tamb = 25 C VDD(1V8) = 1.8 V; Vi(VBAT) = 3.0 V Power-down mode; RTC clock = 32 kHz (from RTCX pins); Tamb = 25 C VDD(1V8) = 1.8 V; Vi(VBAT) = 2.5 V VDD(1V8) = 1.8 V; Vi(VBAT) = 3.0 V Deep power-down mode; RTC off; SRAM off; Tamb = 25 C VDD(1V8) = 1.8 V; Vi(VBAT) = 3.0 V I2C-bus pins VIH VIL Vhys VOL ILI HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS = 3 mA VI = VDD(3V3) VI = 5 V
[15] [10]
-
41 2.5 35
70 25 105
mA A A
-
0.7
-
A
[14]
-
10
15
A
-
7 8
12 12
A A
0.7VDD(3V3) 0
8 -
-
A V
0.3VDD(3V3) V V V A A V
0.5VDD(3V3) 2 10 0.4 4 22 1.8
Oscillator pins Vi(XTAL1) input voltage on pin XTAL1
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Table 5. Static characteristics ...continued Tamb= -40 C to +85 C for commercial applications, unless otherwise specified. Symbol Vo(XTAL2) Vi(RTCX1) Parameter output voltage on pin XTAL2 input voltage on pin RTCX1 Conditions Min 0 0 0 Typ[1] Max 1.8 1.8 1.8 Unit V V V
Vo(RTCX2) output voltage on pin RTCX2
[1] [2] [3] [4] [5] [6] [7] [8] [9]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. Core and internal rail. External rail. If VDD(3V3) < 3.0 V, the I/O pins are not 5 V tolerant, and the ADC input voltage is limited to VDDA = 3.0 V. If VDDA < 3.0 V, the I/O pins are not 5 V tolerant. The RTC typically fails when Vi(VBAT) drops below 1.6 V. Including voltage on outputs in 3-state mode. VDD(3V3) supply voltages must be present. 3-state outputs go into 3-state mode when VDD(3V3) is grounded.
[10] Accounts for 100 mV voltage drop in all supply lines. [11] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [12] Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V. VDDA 3.0 V and VDD(3V3) 3.0 V. [13] Applies to P0.25:16. [14] Battery supply current on pin VBAT. [15] Input leakage current to VSS.
Table 6. ADC static characteristics VDDA = 2.5 V to 3.6 V; Tamb = -40 C to +85 C unless otherwise specified. ADC frequency 4.5 MHz. Symbol VIA Cia ED EL(adj) EO EG ET
[1] [2] [3] [4] [5] [6] [7]
Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error
Conditions
Min 0 [1][2][3] [1][4] [1][5] [1][6] [1][7]
Typ -
Max VDDA 1 1 2 3 0.5 4
Unit V pF LSB LSB LSB % LSB
-
Conditions: VSSA = 0 V, VDDA = 3.3 V and VDD(3V3) = 3.3 V for 10-bit resolution at full speed; VDDA = 2.6 V, VDD(3V3) = 2.6 V for 8-bit resolution at full speed. The ADC is monotonic, there are no missing codes. The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 5. The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 5. The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 5. The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 5. The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 5.
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offset error EO 1023
gain error EG
1022
1021
1020
1019
1018
(2)
7 code out 6
(1)
5
(5)
4
(4)
3
(3)
2
1
1 LSB (ideal) 1018 1019 1020 1021 1022 1023 1024
0 1 offset error EO 2 3 4 5 6 7 VIA (LSBideal)
1 LSB =
VDDA - VSSA 1024
002aac046
(1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve.
Fig 5.
ADC conversion characteristics
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8.1 Power consumption in Deep power-down mode
1.5 IDD(CORE) (A) 1.25
002aae680
1 VDD(1V8) =1.8 V 1.7 V 0.75 1.65 V
0.5 -40
-15
10
35
60 85 Temperature (C)
Test conditions: Deep power-down mode entered; RTC off; SRAM off; Vi(VBAT) = VDD(3V3) = VDDA = 3.3 V.
Fig 6.
Core supply current IDD(CORE) measured at different temperatures and supply voltages
15 IBAT (A) 12.5
RTC on; SRAM on RTC on; SRAM off
002aae681
10
RTC off; SRAM on RTC off; SRAM off
7.5
5 -40
-15
10
35
60 85 Temperature (C)
Test conditions: Deep power-down mode entered; Vi(BAT) = 3.3 V; VDD(1V8) = 1.8 V; VDD(3V3) = VDDA = 3.3 V.
Fig 7.
Battery supply current IBAT measured at different temperatures and conditions
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0.20 IDD(IO) (A) 0.15
002aae682
0.10
0.05
0 -40
-15
10
35
60 85 Temperature (C)
Test conditions: Deep power-down mode entered; RTC off; SRAM off; VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; Vi(BAT) = VDDA = 3.3 V.
Fig 8.
I/O supply current IDD(IO) measured at different temperatures
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9. Dynamic characteristics
Table 7. Dynamic characteristics Tamb = 0 C to 70 C for commercial applications, -40 C to +85 C for industrial applications, VDD(1V8), VDD(3V3) over specified ranges[1]. Symbol External clock fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL tr(o) tf(o) I2C-bus tf(o)
[1] [2] [3]
Parameter oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time output rise time output fall time pins (P0.2 and P0.3) output fall time
Conditions
Min 10 40 Tcy(clk) x 0.4 Tcy(clk) x 0.4 -
Typ[2] 10 10 -
Max 25 100 5 5 -
Unit MHz ns ns ns ns ns ns ns ns
Port pins (except P0.2 and P0.3)
VIH to VIL
20 + 0.1 x Cb[3]
Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. Bus capacitance Cb in pF, from 10 pF to 400 pF.
10. Application information
10.1 XTAL1 input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV (RMS) is needed. For more details see the LPC2101/02/03 User manual UM10161.
LPC2xxx
XTAL1
Ci 100 pF Cg
002aae718
Fig 9.
Slave mode operation of the on-chip oscillator
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10.2 XTAL and RTC Printed Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1 and Cx2, and Cx3 in case of third overtone crystal usage, have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible, in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout.
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11. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 10. Package outline SOT313-2 (LQFP48)
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HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm
D B A
SOT619-7
terminal 1 index area
E
A A1 c
detail X
e1 e 1/2 e 13 L 12 b 24 25 v w
M M
C CAB C y1 C y
e
Eh 1/2 e
e2
1 terminal 1 index area 48 Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 7.1 6.9 Dh 3.45 3.15 E (1) 7.1 6.9 Eh 3.45 3.15 37
36
X 2.5 scale e 0.5 e1 5.5 e2 5.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included OUTLINE VERSION SOT619-7 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 05-10-24 05-10-25
Fig 11. Package outline SOT619-7 (HVQFN48)
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Single-chip 16-bit/32-bit microcontrollers
HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 6 x 6 x 0.85 mm
SOT778-3
D
B
A
terminal 1 index area
E
A A1 c
detail X
C e1 e
13
1/2 e
b
24 25
v w
M M
CAB C
y1 C
y
L
12
e
Eh 1/2 e
e2
1
36 48 37
terminal 1 index area
X 0 2.5 scale 5 mm
Dh
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 1 A1 0.05 0.00 b 0.25 0.15 c 0.2 D (1) 6.1 5.9 Dh 3.95 3.65 E (1) 6.1 5.9 Eh 3.95 3.65 e 0.4 e1 4.4 e2 4.4 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included OUTLINE VERSION SOT778-3 REFERENCES IEC --JEDEC --JEITA --EUROPEAN PROJECTION ISSUE DATE 04-06-16 04-06-23
Fig 12. Package outline SOT778-3 (HVQFN48)
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12. Abbreviations
Table 8. Acronym ADC AMBA APB DCC DSP FIFO FIQ GPIO IAP IRQ ISP PLL PWM SPI SRAM SSI SSP TTL UART VIC Acronym list Description Analog-to-Digital Converter Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Debug Communications Channel Digital Signal Processor First In, First Out Fast Interrupt reQuest General Purpose Input/Output In-Application Programming Interrupt Request In-System Programming Phase-Locked Loop Pulse Width Modulator Serial Peripheral Interface Static Random Access Memory Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Vectored Interrupt Controller
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13. Revision history
Table 9. Revision history Release date 20090602 Data sheet status Product data sheet Change notice Supersedes LPC2101_02_03_3 Document ID LPC2101_02_03_4 Modifications:
* * * * * * * * * *
Section 6.17.4 "Code security (Code Read Protection - CRP)": added description of three CRP levels (applicable to Revision A and higher). Section 6.17.7 "Power control": added description of Deep power-down mode (applicable to Revision A and higher). Section 10.1 "XTAL1 input" added. Section 10.2 "XTAL and RTC Printed Circuit Board (PCB) layout guidelines" added. Figure 6, Figure 7, Figure 8: added power consumption data for Deep power-down mode (applicable to Revision A and higher). Table 3: added table note 7. Table 3: modified description of P0.14, RTCX1, RTCX2, XTAL1, XTAL2, JTAG, and DBGSEL pins. Table 4: modified value for VDD(3V3). Table 5: added and modified values for Vhys. Table 5: Voltage range for pins VDD(3V3) and VDDA extended to 2.6 V. Product data sheet LPC2101_02_03_2 Updated data sheet status to Product data sheet. Table 1 and Table 2: added LPC2102FHN48 and LPC2103FHN48. Table 1, Table 2, Table 3 and related figures: removed LPC2103FA44. Table 3: updated pad descriptions. Table 3: updated description of pin 47, SCL1. Table 3: updated description of pins VDDA and VDD(1V8). Table 4: changed storage temperature range from -40 C/125 C to -65 C/150 C. Table 5: added or modified values for IDD(act), IDD(pd), IBATpd, IBATact. Table 5: removed "CCLK = 10 MHz" and associated values for IDD(act). Section 5: added Figure 3. Section 11: added Figure 11. Preliminary data sheet Preliminary data sheet LPC2101_02_03_1 -
LPC2101_02_03_3 Modifications:
20081007
* * * * * * * * * * *
LPC2101_02_03_2 LPC2101_02_03_1
20071218 20060118
LPC2101_02_03_4
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14. Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
14.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
15. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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Single-chip 16-bit/32-bit microcontrollers
16. Contents
1 2 2.1 2.2 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.5.1 6.6 6.7 6.7.1 6.8 6.8.1 6.9 6.9.1 6.10 6.10.1 6.11 6.11.1 6.12 6.12.1 6.13 6.13.1 6.14 6.14.1 6.15 6.15.1 6.16 6.16.1 6.17 6.17.1 6.17.2 6.17.3 6.17.4 6.17.5 6.17.6 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Enhanced features . . . . . . . . . . . . . . . . . . . . . . 1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . 10 Architectural overview. . . . . . . . . . . . . . . . . . . 10 On-chip flash program memory . . . . . . . . . . . 10 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 11 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 12 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 12 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 12 Fast general purpose parallel I/O . . . . . . . . . . 13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C-bus serial I/O controllers. . . . . . . . . . . . . . 14 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 14 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SSP serial I/O controller . . . . . . . . . . . . . . . . . 15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 General purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 General purpose 16-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 System control . . . . . . . . . . . . . . . . . . . . . . . . 17 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 17 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reset and wake-up timer . . . . . . . . . . . . . . . . 18 Code security (Code Read Protection - CRP) 19 External interrupt inputs . . . . . . . . . . . . . . . . . 19 Memory mapping control . . . . . . . . . . . . . . . . 19 6.17.7 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.8 APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18 Emulation and debugging. . . . . . . . . . . . . . . . 6.18.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 6.18.2 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 8 Static characteristics . . . . . . . . . . . . . . . . . . . 8.1 Power consumption in Deep power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Application information . . . . . . . . . . . . . . . . . 10.1 XTAL1 input . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 XTAL and RTC Printed Circuit Board (PCB) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information . . . . . . . . . . . . . . . . . . . . . . 14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information . . . . . . . . . . . . . . . . . . . . 16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 20 20 21 21 22 23 27 29 29 29 30 31 34 35 36 36 36 36 36 36 37
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 June 2009 Document identifier: LPC2101_02_03_4

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